The open commons that every POWER implementation builds on — synthesizable CPU cores, open firmware stacks, and active ISA development. All governed by the community, freely available under open source licenses.
The POWER ISA has been openly licensed since 2019. These projects are the community's implementations of that open architecture — the reference cores, firmware stacks, and ISA extensions that prove the standard works and give every builder a starting point.
These open source projects are the standards layer. For consortium programs that build actual hardware and sovereign computing platforms on top of this foundation, see Implementation Programs →
A fully open source, synthesizable POWER ISA soft-core that runs Linux on FPGA — and has been taped out as a real ASIC via the OpenROAD toolchain. The reference implementation for the open POWER ISA.
Build a SmartNIC-class DPU without Arm or royalties.
IBM's 4-thread in-order processor from the PowerEN networking SoC and BlueGene/Q supercomputer — open-sourced to the community. The open-ISA, royalty-free alternative to proprietary Arm-based SmartNIC CPUs. Four hardware threads keep forwarding pipelines full without out-of-order overhead. Runs Linux and SONiC natively. Apache 2.0.
A new 32-bit POWER ISA processor built on the VexRiscv framework — lightweight, embedded-class, and already taped out as real silicon via the efabless Caravel MPW shuttle on SkyWater 130nm. The easiest path to a real POWER ISA chip using fully open-source tools. Runs LiteX BIOS, MicroPython, and CoreMark. Apache 2.0.
An open source out-of-order POWER ISA processor core — a commercial-grade superscalar design available to the community. Being updated to full POWER ISA compliance in collaboration with POWER Commons and LibrePOWER.
Skiboot (OPAL), Petitboot, and Heads — a complete open firmware stack from power-on through secure boot. No proprietary blobs, no management engines. Full transparency from first instruction to OS handoff.
Active ISA development through the AI Special Integration Group — defining new matrix, vector, and inference extensions to the POWER ISA that keep the architecture at the frontier of AI accelerated computing.
An open source Baseboard Management Controller for POWER-based servers built on OpenBMC — enabling transparent, auditable firmware for out-of-band server management without proprietary blobs.
Explore the full OpenPOWER Foundation GitHub organization — specifications, tooling, reference implementations, and community projects.
These projects are open to all — join a working group to help shape the POWER ISA, contribute code, or participate in the AI Special Integration Group defining the next generation of matrix and inference extensions.
