Community-developed, fully open source implementations of the POWER ISA — from synthesizable soft-cores to out-of-order processors. Free to use, study, modify, and deploy under open source licenses.
Four open-source POWER ISA processor cores covering every design point: Microwatt for FPGA prototyping, A2I (4-thread, in-order) for SmartNIC/DPU/SONiC networking, A2O for server-class out-of-order compute, and A2P — a 32-bit lightweight core already taped out in real silicon via the efabless open shuttle. Apache 2.0, no licensing fee.
The Enterprise Sovereignty Initiative uses a licensed IBM POWER design as its production base — a commercial-grade CPU proven at scale in the world's most demanding environments. Open Silicon is the community R&D layer; ESI is the organized commercial deployment. They are complementary, not competing.
From FPGA prototyping to BlueGene/Q-heritage networking silicon to out-of-order server compute to 32-bit embedded tapeouts — all Apache 2.0, all on GitHub, all implementing the open POWER ISA.
A fully synthesizable, minimal-footprint POWER ISA soft-core designed to run Linux on FPGA — and proven in real silicon. Microwatt was taped out as an actual ASIC through the OpenROAD open EDA toolchain, making it the reference end-to-end demonstration of the open POWER ISA: from spec to RTL to silicon. The 2025 OPF Hackathon attracted teams extending Microwatt with new capabilities across AI, cryptography, and custom accelerators.
Build a SmartNIC-class DPU without Arm or royalties.
IBM's original "wire-speed processor" — designed for the PowerEN edge-of-network SoC and later selected as the compute core for the BlueGene/Q supercomputer (18 cores per chip at 1.6 GHz). A2I is a 4-thread, in-order processor: four hardware threads keep forwarding pipelines continuously fed without the area and power overhead of out-of-order speculation — exactly the profile networking silicon demands. Commercial SmartNIC DPUs rely on proprietary Arm CPUs with ISA licensing strings attached. A2I is the open-source, open-ISA alternative: same Linux and SONiC compatibility, zero ISA royalties, RTL you own outright. For ESUN networking deployments and SONiC switching platforms, A2I delivers the control-plane CPU with no proprietary CPU overhead — leaving die area and power budget for the custom forwarding ASICs that differentiate the product.
An open source out-of-order POWER ISA processor core with commercial heritage — originally designed by IBM for embedded and storage applications and open-sourced to the community. The A2O is a fully out-of-order, superscalar design capable of running production Linux workloads. It is actively being updated to full POWER ISA compliance in collaboration with POWER Commons and LibrePOWER — bringing it to the current open ISA specification.
"Back to the 90s" — POWER ISA on VexRiscv. Already in silicon.
A2P is a new open-source 32-bit POWER ISA processor built by grafting POWER ISA instruction semantics onto the VexRiscv framework — not a simplified A2I or A2O, but a clean-sheet lightweight core. It integrates into LiteX SoCs via Wishbone, runs BIOS, MicroPython, and CoreMark, and has already been taped out as real silicon through the efabless Caravel multi-project wafer shuttle on SkyWater 130nm — making it the most accessible POWER ISA core for open silicon experimentation. If you want to tape out a POWER ISA chip through the free efabless shuttle program with a fully open toolchain (OpenLane, DFFRAM, SkyWater PDK), A2P is your starting point.
Four cores covering distinct design points — from open SmartNIC/DPU networking to FPGA prototyping to server-class compute to embedded tapeouts. A practical starting point for teams building on POWER without a commercial silicon contract.
A2I is the open-source CPU for teams building SmartNIC DPUs without Arm. Same in-order control-plane profile, Linux and SONiC compatible, zero ISA royalties — and RTL you own outright. The obvious core for ESUN networking and open switching silicon.
Run a complete POWER Linux system on an FPGA today — no fab, no silicon contract required. Microwatt boots on Arty, OrangeCrab, and other common boards.
Study a real, production-caliber ISA implementation in open RTL. Used in computer architecture courses and research labs at universities worldwide.
Start from a validated POWER core rather than building from scratch. Integrate Microwatt or A2O into a custom SoC with proprietary accelerators around it.
Reference implementations that prove the open POWER ISA specification is correct, complete, and implementable — the runnable spec for the architecture.
The Open Silicon Program is the community R&D and reference layer — proving the ISA, advancing open implementations, and giving any organization a starting point for POWER-based silicon development.
The ESI is the organized commercial deployment layer — using a licensed IBM POWER design as a production-proven base, manufactured at US fabs, and delivered to regulated enterprises as certified bare metal platforms.
All four cores are actively developed on GitHub. Join the community, open a pull request, or participate in the POWER ISA compliance effort through the OPF working groups.
