A collaborative program where member organizations pool engineering talent and funding to develop open source IP for sovereign compute — from processor cores to AI accelerators. Shared cost. Shared ownership. Production-grade output.
The proven collaborative engineering model that built the open silicon ecosystem
Four principles that make collaborative open silicon development viable
Steering Members assign full-time engineers to the program. Those engineers work within shared working groups under OPF governance — accelerating roadmaps that benefit all members without one company bearing full cost.
Each working group has a defined charter, technical lead, and release cadence. Group Members fund specific WGs aligned to their product roadmap. Output is open source RTL, verification suites, toolchain support, or firmware — not research papers.
All IP produced by the program is released under an open license. Every member gets equal access to the output — including proprietary optimizations and derivative works built on top of the open core.
Steering Members hold seats on the Technical Steering Committee and participate in quarterly roadmap planning. Working group charters require Steering Member approval before launch — preventing scope creep and ensuring commercial viability.
Six technical programs. Each with a defined charter, technical lead, and open source output.
Maintain the POWER ISA compliance test suite and develop open RTL reference cores (Microwatt family). Includes formal verification, simulation frameworks, and FPGA targets for compliance validation.
Develop and maintain open source EDA flows for POWER silicon tape-out — from synthesis through place-and-route to signoff. Integrate partner EDA toolchains into a unified CI pipeline.
Extend POWER ISA with open AI/ML acceleration primitives. Design open inference accelerator IP blocks compatible with UCIe chiplet attachment for custom AI deployments in sovereign environments.
Develop open firmware infrastructure for POWER platforms — secure boot chains, Caliptra root-of-trust integration, OpenBMC BSPs, and UEFI payloads. Required for CMMC L3+ and CNSA 2.0 compliance.
Define POWER-native chiplet interface standards on the UCIe physical layer. Enable member organizations to develop interoperable chiplets — memory controllers, accelerators, I/O — that attach to open POWER compute tiles.
Maintain and extend the POWER Compatibility Layer (PCL) — Box64 and QEMU user-mode stack — enabling existing Linux binaries to run on ppc64le without recompilation. Includes CI testing across major Linux distributions.
Three tiers built for different levels of investment and involvement
Annual contribution · Board seat included
Annual contribution · Per working group
Annual contribution · Lighter engagement
Silicon R&D is expensive. The assignee model spreads engineering cost across members while every member gets access to the complete output — not just the pieces they funded.
Open source RTL means any member can build, modify, or manufacture independently. No EDA tool dependency, no foundry exclusivity, no licensing gate on derivatives. The RTL is yours to own and extend.
Every IP block developed here is audit-ready: open source means governments and regulators can inspect every gate. Critical for defense, national AI programs, and regulated infrastructure.
Working group members get early access to verification suites, PDK integrations, and reference flows. Collapse your tape-out timeline by building on proven open foundations.
The first cohort of Steering and Group Members shapes the working group charters, technical priorities, and governance structure — permanently recognized as program founders.
Open Silicon Development members have a pathway into the ESI program — using open IP as the differentiation layer in a licensed POWER chiplet for sovereign AI deployments.
We're recruiting founding Steering and Group Members now. Early members shape the working group charters and technical priorities for the program.
