A Linux Foundation Project
IBM POWER9 CPU die

The Open Architecture for
Sovereign AI Infrastructure

The OpenPOWER Foundation advances the POWER architecture as an open standard — giving enterprises full sovereignty over their AI infrastructure, with no vendor lock-in, built-in AI acceleration, and the reliability the world's most demanding workloads require.

Built for
Sovereign Infrastructure
AI-Native ISA
Enterprise Reliability
IBM POWER9 CPU Die
Open
Royalty-free ISA · Apache 2.0 · No vendor lock-in
Stable
30+ year binary compatibility · One ISA · No fragmentation
Performant
SMT8 · High memory bandwidth · Native MMA AI acceleration
Supported
Community · Working groups · Compliance programs · Patent coverage
POWER Architecture

Built for Enterprise. Open by Design.

When your workload is regulated, mission-critical, or classified — you cannot outsource your compute stack to a foreign vendor's cloud. POWER gives you AI performance, memory scale, and hardware isolation entirely within your own infrastructure.

AI Inference Inside Your Perimeter

The Matrix Math Accelerator (MMA) is built directly into the POWER ISA — not a bolt-on GPU. Run LLM inference, fraud detection, and medical imaging models on your own hardware, inside your security boundary. Patient records and trading data never leave your data centre to reach an AI API.

ISA Specification →

Memory Bandwidth That Scales With Your Models

A 70B-parameter model requires ~140 GB of memory just to load — and conventional DIMM slots hit a hard ceiling. The Open Memory Interface (OMI) lets you scale memory capacity and bandwidth independently of the CPU, at DDR5 speeds, using hardware from any vendor. No proprietary memory bus, no single-source dependency.

OMI Specification →
Initiative

OpenCAPI: The Open NVLink

OpenCAPI connected FPGAs, HSMs, and AI accelerators directly to the POWER processor memory fabric — bypassing PCIe entirely, the same way NVIDIA's proprietary NVLink does. The specs are publicly archived. The FPGA reference designs are on GitHub. What's missing is an IP license grant from the original consortium founders — IBM, AMD/Xilinx, NVIDIA/Mellanox, Micron — to OPF members.

Support this initiative →

Hardware-Enforced Workload Isolation

POWER's Logical Partitioning (LPAR) is defined in the ISA itself — not a hypervisor policy. A trading system and a compliance engine on the same physical server are cryptographically separated at the processor level. Each partition has its own privilege domain, memory protection, and interrupt handling, enforced by the architecture. This is how POWER runs in central banks, payment networks, and classified government systems.

Technical Overview →
Why POWER

Built for Sovereign AI Infrastructure

POWER is the architecture of choice when the workload is enterprise AI, mission-critical data, or production data center infrastructure — open by design, proven at scale, and ready today.

Open by Design

Full sovereignty over your infrastructure stack

Royalty-free, open ISAAny OpenPOWER member can implement POWER in silicon without royalties or vendor approval — full ownership of your compute foundation from the instruction set up.
Open, auditable firmwareThe full firmware stack (Skiboot/Petitboot) is open source and inspectable. Every layer of your infrastructure is transparent — no hidden management engines.
MMA: AI acceleration built into the ISAMatrix Math Assist instructions in the latest POWER ISA deliver hardware-level matrix compute natively — AI acceleration that is part of the architecture, not an add-on.
Member-governed roadmapThe POWER ISA evolves through the OpenPOWER Foundation — governed by its members, not a single corporation's product strategy.
OpenCAPI & OMI interconnectsOpen high-speed interconnect standards let you attach memory, accelerators, and custom silicon on your terms — no proprietary bus licences required.
Full IBM patent coverageAny OpenPOWER member who designs a POWER ISA-compliant processor receives full patent coverage from IBM — removing legal risk from your silicon development programme and letting your team focus on innovation.
Enterprise AI & Data Center

Production-grade, at scale, today

Memory bandwidth for AI at scaleThe POWER architecture delivers exceptional memory bandwidth and up to 8 hardware threads per core — critical for large model inference, in-memory databases, and real-time analytics.
The full enterprise software stack, shipping nowLinux, SAP HANA, Oracle DB, OpenJDK, PyTorch, LLVM, GCC, and hundreds of enterprise packages are fully supported and optimized for POWER.
Decades of enterprise RASFinancial services, healthcare, and government depend on POWER's Reliability, Availability, and Serviceability — validated over decades in the world's most demanding environments.
Production silicon in data centers globallyPOWER ISA-compliant systems run mission-critical workloads in data centers around the world. When your AI infrastructure has zero tolerance for downtime, you need an architecture with that track record.
Enterprise support from day oneIBM, Red Hat, and SUSE provide the enterprise-grade support contracts that regulated industries and national infrastructure operators require before any deployment.

Why Now

AI and Accelerated Computing

AI has reshaped the compute landscape. POWER's open architecture and MMA instructions give developers and enterprises the freedom to optimize at every layer of the stack.

Enterprise HPC Demand is Rising

Mission-critical HPC requires a portable, production-ready stack. POWER delivers proven performance for scientific computing, financial modeling, and real-time analytics.

Open Ecosystem, No Lock-in

With a royalty-free ISA and a growing global membership, OpenPOWER is the only open architecture with a full enterprise software and hardware ecosystem ready for deployment today.

The Full Stack is Ready

Decades of investment in POWER hardware, open firmware, and software mean you can deploy with confidence — no waiting for ecosystem maturity.

Engage with OpenPOWER

Build on POWER. Bring your roadmap inside the ecosystem.

Whether you ship products on POWER today or want to start, there's a path for you — from co-developing next-generation silicon to deploying production infrastructure.

Enterprise

Already running POWER?

Extend your POWER infrastructure investment into the next generation. Shape the ISA roadmap, co-develop AI extensions, and access early silicon through the Enterprise Sovereignty Initiative.

Explore ESI Indicate Interest
Hyperscaler

Diversify beyond proprietary ISAs

A royalty-free, open architecture with decades of production validation. ESI gives hyperscalers a differentiated silicon path — UCIe chiplet interfaces, licensed IBM POWER IP, and governance rights over the roadmap.

Learn about ESI Indicate Interest
OCP ODM · Systems Integrator

Open platform silicon for OCP-native designs

Design OCP-compliant servers and accelerator trays with a fully open ISA at the core. No per-unit royalties, no black-box firmware — and a growing community of operators who already buy POWER-based infrastructure.

ESI for ODMs Indicate Interest
Fabless Semiconductor

Tape out on open silicon — no ISA tax

Start from open-source synthesizable POWER ISA cores (Microwatt, A2I, A2O) or license IBM POWER chiplets via ESI. Either path gives you a production-proven ISA without royalty entanglement or vendor dependency.

Open Silicon Program Indicate Interest

Not sure which track fits? Start here.

Talk to the OpenPOWER team →
Open Source

Open Standards Layer

The open commons every POWER implementation builds on — synthesizable cores, firmware stacks, and active ISA development. Free to all, governed by the community. View all open source →

Soft Core · VHDL

Microwatt

A fully open source, synthesizable POWER ISA soft-core that runs Linux on FPGA — and has been taped out as a real ASIC via the OpenROAD toolchain. The reference implementation for the open POWER ISA.

Processor Core · Verilog

A2O Core

An open source out-of-order POWER ISA processor core — a commercial-grade design available to the community. Being updated to full POWER ISA compliance in collaboration with POWER Commons and LibrePOWER.

ISA Development · AI SIG

ISA AI Extensions

Active ISA development through the AI Special Integration Group — defining new matrix, vector, and inference extensions to the POWER ISA that keep the architecture at the frontier of AI accelerated computing.

Firmware · C / Assembly

Open Firmware Stack

Skiboot (OPAL), Petitboot, and Heads — a complete open firmware stack from power-on through secure boot. No proprietary blobs, no management engines. Full transparency from first instruction to OS handoff.

Hardware · Open Design

Open Reference Designs

Open hardware reference designs for POWER-based systems — from workstations to rack servers — developed collaboratively by OpenPOWER member organizations and available to the broader community.

AI Inference · Open Silicon

OpenAIU Accelerator

An open AI inference SoC built on the POWER ISA — combining 32 AI accelerator cores with a 4× Microwatt control cluster. Fully open from ISA to GDSII.

Processor · POWER ISA

OpenCore Processor

A fully open POWER ISA compliant processor core — royalty-free, auditable, and available for sovereign chip design programs worldwide.

Consortium · Regulated Industries

Enterprise Sovereignty Initiative

A consortium program enabling regulated industries to co-fund and co-own sovereign AI compute infrastructure — auditable hardware, open firmware, no vendor lock-in.

All Projects · GitHub

View All on GitHub

Explore the full OpenPOWER Foundation GitHub organization — specifications, tooling, reference implementations, and community projects.

Latest Blog + News

🌐

OpenPOWER Summit 2025: Recap and Highlights

OPF Staff | Blog

Hundreds of developers, researchers, and hardware engineers gathered to share advances in POWER architecture, open firmware, and the growing AI acceleration ecosystem...

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